The circuit diagram shown here is an example of a synchronous boost circuit with SiC MOSFET bridge structure when the LS switch is conducting. The circuit diagram includes the parasitic capacitance, inductance, resistance of SiC MOSFET, as well as the gate current (green line) generated by the VDS and ID changes of HS and LS SiC MOSFET.

Voltage changes caused by ID changes

The change in ID will result in the following voltage formula (1):

This is because the voltage generated by ID flowing through the parasitic inductance at the source of SiC MOSFET is caused by (I) in the circuit diagram. This voltage will cause current (I) to flow through.

Current variation caused by VDS variation

Taking HS as an example, when SiC MOSFET is turned off and VDS changes, a current ICGD will be generated in the gate rain parasitic capacitance CGD. As shown in the circuit diagram, this current is divided into the current flowing through the gate source parasitic capacitance CGS side ICGD1: (II) -1 and the current flowing through the gate circuit side ICGD2: (II) -2. When VDS starts to change, the impedance on the gate circuit side is relatively high, so most ICGDs are on the CGS side. At this time, ICGD1 is shown in formula (2).

From the formula, it can be seen that when CGD is large or the ratio of CGD/CGS decreases, ICGD1 will increase.

DVDS/dt and dID/dt can be both positive and negative, so the polarity of the current and voltage they generate during turn on and turn off is different.